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33
PRELIMINARY
CY7C1041AV33/ GVT73256A16
256K x 16 Static RAM
Features
* * * * * * * * * * * Fast access times: 10, 12 ns Fast OE access times: 5, 6, and 7 ns Single +3.3V 0.3V power supply Fully static--no clock or timing strobes necessary All inputs and outputs are TTL-compatible Three state outputs Center power and ground pins for greater noise immunity Easy memory expansion with CE and OE options Automatic CE power-down High-performance, low power consumption, CMOS double-poly, double-metal process Packaged in 44-pin, 400-mil SOJ and 44-pin, 400-mil TSOP
Functional Description
The CY7C1049AV33\GVT73512A8 is organized as a 262,144 x 16 SRAM using a four-transistor memory cell with a high-performance, silicon gate, low-power CMOS process. Cypress SRAMs are fabricated using double-layer polysilicon, double-layer metal technology. This device offers center power and ground pins for improved performance and noise immunity. Static design eliminates the need for external clocks or timing strobes. For increased system flexibility and eliminating bus contention problems, this device offers Chip Enable (CE), separate Byte Enable controls (BLE and BHE) and Output Enable (OE) with this organization. The device offers a low-power standby mode when chip is not selected. This allows system designers to meet low standby power requirements.
Functional Block Diagram
VCC VSS BLE#
Pin Configuration
SOJ/TSOP II Top View
A0
DQ1
ADDRESS BUFFER
MEMORY ARRAY 512 ROWS X 256 X 16 COLUMNS
DQ8
DQ9
DQ16
A16
COLUMN DECODER
POWER DOWN
CE# BHE# WE# OE#
A0 A1 A2 A3 A4 CE DQ1 DQ2 DQ3 DQ4 VCC VSS DQ5 DQ6 DQ7 DQ8 WE A5 A6 A7 A8 A9
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A17 A16 A15 OE BHE BLE DQ16 DQ15 DQ14 DQ13 VSS VCC DQ12 DQ11 DQ10 DQ9 NC A14 A13 A12 A11 A10
ROW DECODER
Selection Guide
CY7C1049AV33-10/ GVT73512A8-10 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA) Com'l/Ind'l Com'l L 10 240 10 3.0 CY7C1049AV33-12/ GVT73512A8-12 12 210 10 3.0
Cypress Semiconductor Corporation
*
3901 North First Street
I/O CONTROL
*
San Jose
*
CA 95134
*
408-943-2600 June 15, 2000
PRELIMINARY
Truth Table
Mode Low Byte Read (DQ1-DQ8) High Byte Read (DQ 9-DQ16) Word Read (DQ1-DQ 16) Low Byte Write (DQ1-DQ8) High Byte Write (DQ 9-DQ16) Word Write (DQ1-DQ16) Output Disable Standby CE L L L L L L L L H WE H H H L L L X H X OE L L L X X X X H X BLE L H L L H L H X X BHE H L L H L L H X X DQ1-D8 Q High-Z Q D High-Z D High-Z High-Z High-Z
CY7C1041AV33/ GVT73256A16
DQ 9-D16 High-Z Q Q High-Z D D High-Z High-Z High-Z
POWER Active Active Active Active Active Active Active Active Standby
Pin Descriptions
SOJ & TSOP Pin Numbers 1, 2, 3, 4, 5, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 42, 43, 44 17 6 Pin Name A0-A17 Type Input Description Addresses Inputs: These inputs determine which cell is addressed.
WE CE
Input Input
Write Enable: This input determines if the cycle is a READ or WRITE cycle. WE is LOW for a WRITE cycle and HIGH for a READ cycle. Chip Enable: This active LOW input is used to enable the device. When CE is LOW, the chip is selected. When CE is HIGH, the chip is disabled and automatically goes into standby power mode. Byte Enable: These active LOW inputs allow individual bytes to be written or read. When BLE is LOW, the data is written to or read from the lower byte (DQ1-DQ8). When BHE is LOW, the data is written to or read from the higher byte (DQ 9-DQ16). Output Enable: This active LOW input enables the output drivers. SRAM Data I/O: Data inputs and data outputs. Lower byte is DQ1-DQ8 and upper byte is DQ9-DQ16. Power Supply: 3.3V 0.3V%. Ground. Power Dissipation ......................................................... 1.0W Short Circuit Output Current ....................................... 50 mA
39, 40
BLE, BHE
Input
41 7, 8, 9, 10, 13, 14, 15, 16, 29, 30, 31, 32, 35, 36, 37, 38 11, 33 12, 34
OE DQ 1-DQ16
Input Input/ Output Supply Supply
VCC VSS
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Voltage on VCC Supply Relative to VSS ......... -0.5V to +4.6V VIN ...........................................................-0.5V to VCC+0.5V Storage Temperature (plastic)........................-55C to +125 Junction Temperature ..................................................+125
Note: 1. TA is the "Instant On" case temperature.
Operating Range
Range Commercial Industrial Ambient Temperature[1] 0C to +70C -40C to +85C VCC 3.3V 0.3V
2
PRELIMINARY
Electrical Characteristics Over the Operating Range
Parameter VIH VIl ILI ILO VOH VOL VCC Parameter ICC ISB1 ISB2 Description Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Supply Voltage
[2] [2] [2] [2, 3] [2, 3]
CY7C1041AV33/ GVT73256A16
Conditions
Min. 2.2 -0.5
Max. VCC+0.5 0.8 5 5 0.4
Unit V V A A V V V
0V < VIN < VCC Output(s) disabled, 0V < VOUT < VCC IOH = -4.0 mA IOL = 8.0 mA
-5 -5 2.4 3.0
3.6
Description
Conditions
Power std. low std. low std. low
Typ. 90 25 0.1
-10 240 240 70 70 10 3.0
-12 210 210 60 60 10 3.0
Unit mA mA mA
Power Supply Device selected; CE < VIL; VCC = Max.; Current: Operating[4, 5] f = fMAX; outputs open TTL Standby
[5]
CE > V IH; VCC = Max.; f = fMAX CE1 > VCC - 0.2; VCC = Max.; all other inputs < VSS + 0.2 or > VCC - 0.2; all inputs static; f = 0
CMOS Standby[5]
Capacitance[6]
Parameter CI CI/O Description Input Capacitance Input/Output Capacitance (DQ) Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Max. 6 8 Unit pF pF
Note: 2. All voltages referenced to VSS (GND). 3. Overshoot: VIH < +6.0V for t < tRC /2. Undershoot: VIL < -2.0V for t < tRC /2 4. ICC is given with no output current. ICC increases with greater output loading and faster cycle times. 5. Typical values are measured at 3.3V, 25C, and 20 ns cycle time. 6. This parameter is sampled.
AC Test Loads and Waveforms
3.3V
DQ Z 0 = 50 50 Vt = 1.5V 30 pF
ALL INPUT PULSES 3.3V 90% 90% 10% 1.5 ns Fall Time: 1V/ns 0V 10%
317 DQ 351 5 pF
Rise Time: 1V/ns
(a)
(b)
3
PRELIMINARY
Switching Characteristics[5] Over the Operating Range
7C1041AV33-10/ GVT73256A16-10 Parameter READ CYCLE tRC tAA tACE tOH tLZCE tHZCE tAOE tLZOE tHZOE tABE tLZBE tHZBE tPU tPD WRITE CYCLE tWC tCW tAW tAS tAH tWP2 tWP1 tDS tDH tLZWE tHZWE tBW WRITE Cycle Time Chip Enable to End of Write Address Valid to End of Write, with OE HIGH Address Set-up Time Address Hold from End of Write WRITE Pulse Width WRITE Pulse Width, with OE HIGH Data Set-up Time Data Hold Time Write Disable to Output in Low-Z Write Enable to Output in High-Z Byte Enable to End of Write
[6, 7] [6, 7, 8]
CY7C1041AV33/ GVT73256A16
7C1041AV33-12/ GVT73256A16-12 Min. 12 Max. Unit ns 102 12 3 3 ns ns ns ns 6 6 0 6 6 0 6 0 12 12 8 8 0 0 10 8 6 0 4 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 6 8 ns ns
Description READ Cycle Time Address Access Time Chip Enable Access Time Output Hold from Address Change Chip Enable to Output in Low-Z Output Enable Access Time Output Enable to Output in Low-Z Output Enable to Output in High-Z Byte Enable Access Time Byte Enable to Output in Low-Z[6, 7] Byte Disable to Output in High-Z Chip Enable to Power-up Time
[6, 7, 8] [6] [6, 8] [6, 7] [6, 7, 8]
Min. 10
Max.
10 10 3 3 5 5 0 5 5 0 5 0 10 10 8 8 0 0 10 8 5 0 3 5 8
Chip Disable to Output in High-Z
Chip Disable to Power-down Time[6]
Data Retention Characteristics Over the Operating Range (For L version only)
Parameter VDR ICCDR
[9]
Description VCC for Data Retention Data Retention Current
Conditions VCC = 2V CE > VCC - 0.2V; all other inputs < VSS + 0.2 or VCC = 3V >VCC - 0.2; all inputs static; f = 0
Min. 2.0
Typ. 0.2 0.3
Max. 1.6 2.4
Unit V mA mA ns ns
tCDR[6] tR
[6, 10]
Chip Deselect to Data Retention Time Operation Recovery Time
0 tRC
Notes: 7. At any given temperature and voltage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE. 8. Output loading is specified with CL=5 pF as in AC Test Loads. Transition is measured 500mV from steady state voltage. 9. Capacitance derating applies to capacitance different from the load capacitance shown in AC Test Loads. 10. t RC = Read Cycle Time.
4
PRELIMINARY
Low VCC Data Retention Waveform
DATA RETENTION MODE
CY7C1041AV33/ GVT73256A16
VCC CE# V IH V IL
tC D R
3.0V
VDR
3.0V tR C
Switching Waveforms
Read Cycle No. 1[11, 12]
t
RC
ADDR
tAA tOH
VALID
Q
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2[7, 11, 13, 14]
t
RC
CE#
tABE tHZCE
BLE# BHE#
t tLZOE
AOE
t
HZBE
OE#
tLZBE tACE tLZCE tHZOE
Q
HIGH Z
DATA VALID DON'T CARE UNDEFINED
Notes: 11. WE is HIGH for read cycle. 12. Device is continuously selected. Chip Enable and Output Enables are held in their active state. 13. Address valid prior to or coincident with latest occurring chip enable. 14. Chip Enable and Write Enable can initiate and terminate a write cycle.
5
PRELIMINARY
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled with OE Active LOW)[9, 7, 14]
t
CY7C1041AV33/ GVT73256A16
WC
ADDR
tA W t tA H
CW
CE#
tB W
BLE# BHE# WE#
t
AS
tW P 2
t
DS
t
DH
D
tH Z W E
DATA VALID
tL Z W E
Q
HIGH Z
Write Cycle No. 2 (WE Controlled with OE Inactive HIGH)[9, 14]
tW C
ADDR
tA W tC W tA H
CE#
tB W
BLE# BHE#
tA S tW P 1
WE#
tD S tD H
D Q
DATA VALID HIGH Z
6
PRELIMINARY
Switching Waveforms (continued)
Write Cycle No. 3 (CE Controlled)[9, 14]
t
CY7C1041AV33/ GVT73256A16
WC
ADDR
t t
AW
t
t
AH
AS
CW
CE#
t
BW
BLE# BHE#
t
WP1
WE#
t
DS
t
DH
D
DATA VALID HIGH Z
DON'T CARE
Q
Write Cycle No. 4 (Byte Enable Controlled)[9, 14]
t
WC
ADDR
t t
AW
t
t
AH
AS
BW
BLE# BHE# CE#
t
CW
t
WP1
WE#
t
DS
t
DH
D
DATA VALID HIGH Z
DON'T CARE
Q
7
PRELIMINARY
Ordering Information
Speed (ns) 10 Ordering Code CY7C1041AV33-10VC GVT73256A16J-10C CY7C1041AV33-10ZC GVT73256A16TS-10C CY7C1041AV33L-10VC GVT73256A16J-10LC CY7C1041AV33L-10ZC GVT73256A16TS-10LC 12 CY7C1041AV33-12VC GVT73256A16J-12C CY7C1041AV33-12ZC GVT73256A16TS-12C CY7C1041AV33L-12VC GVT73256A16J-12LC CY7C1041AV33L-12ZC GVT73256A16TS-12LC Document #: 38-00997-** Z44 44-Pin TSOP II V36 36-Lead (400-Mil) Molded SOJ Z44 44-Pin TSOP II V36 36-Lead (400-Mil) Molded SOJ Z44 44-Pin TSOP II V36 36-Lead (400-Mil) Molded SOJ Z44 44-Pin TSOP II Package Name V36 Package Type 36-Lead (400-Mil) Molded SOJ
CY7C1041AV33/ GVT73256A16
Operating Range Commercial
Commercial
Package Diagrams
44-Lead (400-Mil) Molded SOJ V34
51-85082-B
8
PRELIMINARY
Package Diagrams (continued)
44-Pin TSOP II Z44
CY7C1041AV33/ GVT73256A16
51-85087-A
(c) Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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